Design and Implementation of Power-Efficient FSM based UART

Abstract The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of modern generation. Universal Asynchronous Receiver Transmitter (UART) is one most sought-after protocols. This work focuses on implementing and analysing UART for communication. Finite State Machine (FSM) implements baud rate generator, transmitter, receiver modules. Cadence NCSIM was utilized simulation, RTL Compiler used during synthesis using 45 nm 90 General Process Design Kit (GPDK) library files. 9600 bps 50 MHz clock frequency to design UART. increased speed complexity VLSI chip designs has resulted a significant increase power consumption. comparative analysis delay different periods shows an improvement total Power Delay Product (PDP) with increasing periods. Better results were observed comparison library.